troed wrote:However, while I'm positive you're correct in that the MMU and CPU can occupy one or the other of two possible 2-cycle slots respectively, which indeed is the original wakestate hypothesis - and one I think Steven has implemented in Steem SSE - it actually isn't what I have deduced from my black box reverse engineering. Of course, my hypothesis could be false, but the original only allows for two wakestates and we know that there are four.
No. In first place, what I described here in this thread is not an hypothesis, it is a fact. I've seen the silicon. The GLUE and MMU processes, the counters that drive them, the flip-flops of the counters that are initialized by power-up logic. This is the
actual hardware and this, by itself, predicts the four wakestates.
My original article describes two wakeups because I made a couple of mistakes at the time. At that time yes, it was an hypothesis partially based on speculation about the chip internals. That was before I reverse engineered the silicon. My main mistake was a naive oversimplification of the MMU ram slots interleaving process, which I thought it could be clocked by a single bit counter.
So my
original model, indeed allows only two states. But that's only if you take my original model verbatim. Just modify slightly the MMU part of the model and you get all the four states.
... all four wakestates are explained by 0-3 cycle offsets between the GLUE and CPU (the table from the wiki I cited above).
Again. Yes, of course. But what produces that offset between GLUE and CPU? It's MMU. And that is regardless of the whole wakestates issue. The CPU has no choice but to align
exactly (single cycle accuracy) to MMU timing.
Consider the following:
MMU RAM process timing (as seen with the 8 MHz clock):
Cycle 0: starts CPU 2-cycles slot
Cycle 1: ends CPU 2-cycles slot
Cycle 2: starts Video 2-cycles slot
Cycle 3: ends Video 2-cycles slot
Do you see? Any CPU access to the RAM side will align the CPU "NOP" cycle (bus cycles), with those 4 cycles in the above table.
Now GLUE video process timing (as seen with the 8 MHz clock):
Cycle 0: First quarter of the video 2 MHz cycle.
Cycle 1: Second quarter of the video 2 MHz cycle.
Cycle 2: Third quarter of the video 2 MHz cycle.
Cycle 3: Fourth quarter of the video 2 MHz cycle.
Lastly, align GLUE and MMU processes. You have 4 possibilities. Those are your four wakestates.
... and maybe something unexpected: One of the 1040s above (haven't tried the same with the others yet) _always_ - and I mean always - boots in WS3 if a mono monitor is
Interesting ...
A one line sync scroller was done this way - but after sending a screen using this around we quickly realized that it worked almost nowhere and there was no way to get it stable (except via hardware mods). So we scrapped it.
), I'm curious whether you have evidence for either hypothesis.