Sandbox collapse test

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----------------------|DMA, Blitter                                   |-----
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$FFFF8A36.W|RW|BLT_WPL|Words per Line in BOB                 (0:65536)|BLT
$FFFF8A38.W|RW|BLT_LPB|Lines per BOB                         (0:65536)|BLT

$FFFF8A3A.B|RW|BLT_HTO|Halftone Operation %______xx |BLT

 $FFFF8A3A  BLT_HOP  Halftone Operation      bits 1-0 used

   0   all ones ($FFFF)
   1   halftone RAM word
   2   source word
   3   source word AND halftone RAM word

   The HOP result is what the logical operation sees as its
   "source" input. HOP runs first, LOP second.

          |  |       | 0:set all Bits, 1:HTR, 2:SRC, 3:SRC & HTR     |BLT

$FFFF8A3B.B|RW|BLT_LGO|Logical Operation %____xxxx |BLT

 $FFFF8A3B  BLT_LOP  Logical Operation       bits 3-0 used

   S = output of the halftone operation above
   D = current destination word

   $0   all zeros              $8   NOT S AND NOT D   (NOR)
   $1   S AND D                $9   NOT (S XOR D)     (NXOR)
   $2   S AND NOT D            $A   NOT D
   $3   S                      $B   S OR NOT D
   $4   NOT S AND D            $C   NOT S
   $5   D                      $D   NOT S OR D
   $6   S XOR D                $E   NOT (S AND D)     (NAND)
   $7   S OR D                 $F   all ones

          |  |       | (!S AND !D)------------------------------+||| |BLT
          |  |       | (!S AND  D)-------------------------------+|| |BLT
          |  |       | ( S AND !D)--------------------------------+| |BLT
          |  |       | ( S AND  D)---------------------------------+ |BLT

$FFFF8A3C.B|RW|BLT_LNM|Line Number %BHS_xxxx |BLT

 $FFFF8A3C  BLT_LNM  Control                 %BHS_nnnn

   Bit 7   BUSY    write 1 to start the blitter. Reads 1 while a
                   transfer is in progress, cleared when y count
                   reaches 0.
   Bit 6   HOG     0 = share the bus with the CPU, 1 = take the
                   bus for the whole transfer.
   Bit 5   SMUDGE  use source bits 0-3 as the halftone line
                   number instead of bits 3-0 of this register.
   Bit 4   unused. Hardware masks this bit off on write.
   Bits 3-0        halftone line number, 0-15.

   In non-hog mode the blitter runs for 64 bus accesses, then
   hands the bus to the CPU for 64. Writing 0 to bit 7 while the
   CPU owns the bus pauses the blitter; writing 1 resumes it.
   Pausing does not end the transfer, and busy still reads 1.

          |  |       | Busy (1:start Blitter)---------------+|| |||| |BLT
          |  |       | HOG (1:stop CPU when Busy)------------+| |||| |BLT
          |  |       | SMUDGE (use sourcebits 0-3 as HTR num)-+ |||| |BLT
          |  |       | Halftone-RAM number----------------------++++ |BLT

$FFFF8A3D.B|RW|BLT_SKW|SKEW %FN__xxxx |BLT

 $FFFF8A3D  BLT_SKW  Skew                    %FN__nnnn

   Bit 7   FXSR    Force eXtra Source Read
   Bit 6   NFSR    No Final Source Read
   Bits 5-4        unused
   Bits 3-0        skew, 0-15 pixels

          |  |       | FXSR (Force eXtra Source Read)-------+|  |||| |BLT
          |  |       | NFSR (No Final Source Read)-----------+  |||| |BLT
          |  |       | SKEW (shift)-----------------------------++++ |BLT

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