===========#==#=======#===============================================#=====
----------------------|IDE Bus |-----
===========#==#=======#===============================================#=====
$FFF00000.W|RW|IDE_DAT|Data Register |
$FFF00005.B|RW|IDE_ERR|Read:Error / Write:Features Register |
$FFF00009.B|RW|IDE_SCC|Sector count |
$FFF0000D.B|RW|IDE_SNR|Sector number |
$FFF00011.B|RW|IDE_CYL|Cylinder low |
$FFF00015.B|RW|IDE_CYH|Cylinder high |
$FFF00019.B|RW|IDE_H_D|Head/Drive Register |
$FFF0001D.B|RW|IDE_S_C|Read:Status Register/Write:Command Register |
$FFF00039.B|RW|IDE_ALT|Read:Alt Status/Write:Device Control |
===========#==#=======#===============================================#=====
----------------------|Memory Controller, System Control |-----
===========#==#=======#===============================================#=====
$FFFF8001.B|RW|MEM_CTL|Memory Controller |
$FFFF8006.W|RW|SYS_CTL|System Control %MM______ _RS_bB_C |F
| | | Monitor Type (M0,M1)--------++ || || | |F
| | | Monochrome Monitor----------00 || || | |F
| | | RGB Monitor-----------------01 || || | |F
| | | VGA Monitor-----------------10 || || | |F
| | | TV--------------------------11 || || | |F
| | | Reset 0:ignore resetvector------------+| || | |F
| | | STE-compatible-I/O 0:off,1:on----------+ || | |F
| | | Blitterflag 0:on,1:off-------------------+| | |F
| | | Blitterspeed 0:half clock,1:full clock----+ | |F
| | | CPUspeed 0:half clock,1:full clock----------+ |F
$FFFF8007.B|RW|SYS_FBC|Falcon Bus Control %_SB_BS__ |F
| | | Start type 0:cold,1:warm-------------+||||||| |
| | | STe Bus emulation 0:on,1:off----------+|||||| |
| | | Blitter control 0:on,1:off--------------+|||| |
| | | Blitter speed 0:8MHz,1:16MHz-------------+||| |
| | | CPU speed 0:8MHz,1:16MHz--------------------+ |
| | | Verified: EmuTOS bios/machine.c documents all |
| | | five bits and writes $25 (STe bus emulation |
| | | off, 16MHz blitter and CPU). Atari TOS |
| | | 3.06/4.04 bios/startup.S writes the same $25. |
===========#==#=======#===============================================#=====
----------------------|DMA, VIDEL Controller |-----
===========#==#=======#===============================================#=====
$FFFF8201.B|RW|VDL_VBH|Video Base Hi |
$FFFF8203.B|RW|VDL_VBM|Video Base Mi |
$FFFF8205.B|Rw|VDL_VCH|Video Count Hi |
$FFFF8207.B|Rw|VDL_VCM|Video Count Mi |
$FFFF8209.B|Rw|VDL_VCL|Video Count Lo %xxxxxxx_ |
$FFFF820A.B|RW|VDL_SYM|Sync mode %______VS |
| | | Vfrequency 0:60hz(NTSC),1:50Hz(PAL)--------+| |
| | | Sync 0:internal,1:external------------------+ |
$FFFF820D.B|RW|VDL_VBL|Video Base Lo %xxxxxxx_ |STE,F
$FFFF820E.B|RW|VDL_LOF|Line Offset |STE,F
$FFFF820F.B|RW| - |Line Width-1 |STE
$FFFF8210.W|RW|VDL_LWD|Line Width in Words %______xx xxxxxxxx |F
$FFFF8240.W|RW|VDL_STC|ST Palette Register 00 %____rRRR gGGGbBBB |
...........|RW| - |...................... |
$FFFF825E.W|RW| - |ST Palette Register 15 |
$FFFF8260.B|RW|VDL_SSM|ST-Shift-Mode %_____xxx |
| | | 320*200*4---------------------------------000 |
| | | 640*200*2---------------------------------001 |
| | | 640*400*1---------------------------------010 |
===========#==#=======#===============================================#=====
$FFFF8262.B|RW|VDL_TSM|TT-Shift-Mode %_____xxx |TT
| | | ST low 320*200*4----------------------000 |TT
| | | ST medium 640*200*2----------------------001 |TT
| | | ST high 640*400*1----------------------010 |TT
| | | (Falcon rez marker)-----------------------011 |TT
| | | TT medium 640*480*4----------------------100 |TT
| | | (unused)----------------------------------101 |TT
| | | TT high 1280*960*1----------------------110 |TT
| | | TT low 320*480*8----------------------111 |TT
===========#==#=======#===============================================#=====
$FFFF8264.B|RW|VDL_HSH|H-Scroll Hi %____xxxx |F
$FFFF8265.B|RW|VDL_HSL|H-Scroll Lo - clears Line Width %____xxxx |STE,F
$FFFF8266.W|RW|VDL_FSM|Falcon Shift Mode %_____2OT _HV8PPPP |F
| | | 2 Color mode 0:off,1:on----------+|| ||||||| |F
| | | Overlay mode 0:off,1:on-----------+| ||||||| |F
| | | True(high) color 0:off,1:on--------+ ||||||| |F
| | | Hsync 0:internal,1:external-----------+|||||| |F
| | | Vsync 0:internal,1:external------------+||||| |F
| | | 8 Bitplanes 0:off,1:on------------------+|||| |F
| | | falcon Palette 16 of 256 colors----------++++ |F
$FFFF827E.B|RW|STY_DSP|STACY Display State |STB
| | | UNVERIFIED: Atari Compendium only. Not |
| | | referenced by EmuTOS or any available TOS |
| | | source. |
$FFFF8280.W|RW|VDL_HHC|Horizontal Hold Counter %_______x xxxxxxxx |F
$FFFF8282.W|RW|VDL_HHT|Horizontal Hold Timer %_______x xxxxxxxx |F
$FFFF8284.W|RW|VDL_HBB|Horizontal Border Begin %_______x xxxxxxxx |F
$FFFF8286.W|RW|VDL_HBE|Horizontal Border End %_______x xxxxxxxx |F
$FFFF8288.W|RW|VDL_HDB|Horizontal Display Begin %______Hx xxxxxxxx |F
| | | 0:1.Halfline, 1:2.Halfline--------+ |F
$FFFF828A.W|RW|VDL_HDE|Horizontal Display End %_______x xxxxxxxx |F
$FFFF828C.W|RW|VDL_HSS|Horizontal Sync Start %_______x xxxxxxxx |F
$FFFF828E.W|RW|VDL_HFS|Horizontal FS %_______x xxxxxxxx |F
$FFFF8290.W|RW|VDL_HEE|Horizontal EE %_______x xxxxxxxx |F
$FFFF82A0.W|RW|VDL_VFC|Vertical Frequency Counter %_____xxx xxxxxxxx |F
$FFFF82A2.W|RW|VDL_VFT|Vertical Frequency Timer %_____xxx xxxxxxxx |F
$FFFF82A4.W|RW|VDL_VBB|Vertical Border Begin %_____xxx xxxxxxxx |F
$FFFF82A6.W|RW|VDL_VBE|Vertical Border End %_____xxx xxxxxxxx |F
$FFFF82A8.W|RW|VDL_VDB|Vertical Display Begin %_____xxx xxxxxxxx |F
$FFFF82AA.W|RW|VDL_VDE|Vertical Display End %_____xxx xxxxxxxx |F
$FFFF82AC.W|RW|VDL_VSS|Vertical Sync Start %_____xxx xxxxxxxx |F
$FFFF82C0.W|RW|VDL_VCT|Video Control %_______O BHVUSCMM |F
| | | h-base-Offset 0:128cyc,1:64cyc-----+ |||||||| |F
| | | Buswide 0:16bit,1:32bit--------------+||||||| |F
| | | Hsync 0:negative,1:positive-----------+|||||| |F
| | | Vsync 0:negative,1:positive------------+||||| |F
| | | Use FS & EE 0:on,1:off------------------+|||| |F
| | | 15 halfline hSyncs at VBB----------------+||| |F
| | | video Clock 0:32Mhz,1:25.175Mhz-----------+|| |F
| | | Monitor 0:Mono,1:RGB,2:VGA,3:TV------------++ |F
| | | NAMING CHECK: TOS 4.04 (tos3x vsetmode.c) and |F
| | | EmuTOS write video_control to $82C2 and |F
| | | video_clock to $82C0 - the reverse of these |F
| | | two labels. Addresses/bits correct either way.|F
$FFFF82C2.W|RW|VDL_VMD|Video Mode %________ ____xxID |F
| | | Pixclock:4,Divider:4(VGA)/16(STE)/4------00|| |F
| | | Pixclock:2,Divider:2(VGA)/16(STE)/2------01|| |F
| | | Pixclock:1,Divider:2(VGA)/16(STE)/1------10|| |F
| | | (unused)---------------------------------11|| |F
| | | Interlace 0:off,1:on-----------------------+| |F
| | | Double Scan 0:off,1:on----------------------+ |F
===========#==#=======#===============================================#=====
----------------------|TT Palette Registers |-----
===========#==#=======#===============================================#=====
$FFFF8400.W|RW|TT__PAL|TT Palette Register 000 |TT
...........|RW| - |....................... |TT
$FFFF85FE.W|RW| - |TT Palette Register 255 |TT
===========#==#=======#===============================================#=====
----------------------|VIDEL Palette Register |-----
===========#==#=======#===============================================#=====
$FFFF9800.L|RW|VDL_PAL|Palette Register 000 %RRRRRR__ GGGGGG__ |F
...........|RW| - |.................... ________ BBBBBB__ |F
$FFFF98FC.L|RW| - |Palette Register 255 |F
===========#==#=======#===============================================#=====
----------------------|DMA, Blitter |-----
===========#==#=======#===============================================#=====
$FFFF8A00.W|RW|BLT_HTR|Halftone-RAM 00 |BLT
...........|RW| - |............... |BLT
$FFFF8A1E.W|RW| - |Halftone-RAM 15 |BLT
$FFFF8A20.W|RW|BLT_SXI|Source X increment %xxxxxxxx xxxxxxx_ |BLT
$FFFF8A22.W|RW|BLT_SYI|Source Y increment %xxxxxxxx xxxxxxx_ |BLT
$FFFF8A24.L|RW|BLT_SRC|Source Address %xxxxxxxx xxxxxxxx xxxxxxx_ |BLT
$FFFF8A28.W|RW|BLT_EM1|Endmask 1 |BLT
$FFFF8A2A.W|RW|BLT_EM2|Endmask 2 |BLT
$FFFF8A2C.W|RW|BLT_EM3|Endmask 3 |BLT
$FFFF8A2E.W|RW|BLT_DXI|Destination X increment %xxxxxxxx xxxxxxx_ |BLT
$FFFF8A30.W|RW|BLT_DYI|Destination Y increment %xxxxxxxx xxxxxxx_ |BLT
$FFFF8A32.L|RW|BLT_DST|Destination Adr. %xxxxxxxx xxxxxxxx xxxxxxx_ |BLT
$FFFF8A36.W|RW|BLT_WPL|Words per Line in BOB (0:65536)|BLT
$FFFF8A38.W|RW|BLT_LPB|Lines per BOB (0:65536)|BLT
$FFFF8A3A.B|RW|BLT_HTO|Halftone Operation %______xx |BLT
| | | 0:set all Bits, 1:HTR, 2:SRC, 3:SRC & HTR |BLT
$FFFF8A3B.B|RW|BLT_LGO|Logical Operation %____xxxx |BLT
| | | (!S AND !D)------------------------------+||| |BLT
| | | (!S AND D)-------------------------------+|| |BLT
| | | ( S AND !D)--------------------------------+| |BLT
| | | ( S AND D)---------------------------------+ |BLT
$FFFF8A3C.B|RW|BLT_LNM|Line Number %BHS_xxxx |BLT
| | | Busy (1:start Blitter)---------------+|| |||| |BLT
| | | HOG (1:stop CPU when Busy)------------+| |||| |BLT
| | | SMUDGE (use sourcebits 0-3 as HTR num)-+ |||| |BLT
| | | Halftone-RAM number----------------------++++ |BLT
$FFFF8A3D.B|RW|BLT_SKW|SKEW %FN__xxxx |BLT
| | | FXSR (Force eXtra Source Read)-------+| |||| |BLT
| | | NFSR (No Final Source Read)-----------+ |||| |BLT
| | | SKEW (shift)-----------------------------++++ |BLT
BLITTER - FULL BIT DETAIL
Verified against Hatari src/blitter.c (cycle-exact implementation,
partly derived from ijor's reverse engineering and Verilog work).
$FFFF8A3A BLT_HOP Halftone Operation bits 1-0 used
-------------------------------------------------------------------
0 all ones ($FFFF)
1 halftone RAM word
2 source word
3 source word AND halftone RAM word
The HOP result is what the logical operation below sees as its
"source" input. HOP runs first, LOP second.
$FFFF8A3B BLT_LOP Logical Operation bits 3-0 used
-------------------------------------------------------------------
S = output of the halftone operation above
D = current destination word
$0 all zeros $8 NOT S AND NOT D (NOR)
$1 S AND D $9 NOT (S XOR D) (NXOR)
$2 S AND NOT D $A NOT D
$3 S $B S OR NOT D
$4 NOT S AND D $C NOT S
$5 D $D NOT S OR D
$6 S XOR D $E NOT (S AND D) (NAND)
$7 S OR D $F all ones
$FFFF8A3C BLT_LNM Control %BHS_nnnn
-------------------------------------------------------------------
Bit 7 BUSY write 1 to start the blitter. Reads 1 while a
transfer is in progress, cleared when y count
reaches 0.
Bit 6 HOG 0 = share the bus with the CPU, 1 = take the bus
for the whole transfer.
Bit 5 SMUDGE use source bits 0-3 as the halftone line number
instead of bits 3-0 of this register.
Bit 4 unused. Hardware masks this bit off on write.
Bits 3-0 halftone line number, 0-15.
In non-hog mode the blitter runs for 64 bus accesses, then hands
the bus to the CPU for 64. Writing 0 to bit 7 while the CPU owns
the bus pauses the blitter; writing 1 resumes it. Pausing does
not end the transfer, and the busy bit still reads 1.
$FFFF8A3D BLT_SKW Skew %FN__nnnn
-------------------------------------------------------------------
Bit 7 FXSR Force eXtra Source Read
Bit 6 NFSR No Final Source Read
Bits 5-4 unused
Bits 3-0 skew, 0-15 pixels
$FFFF8A00-$FFFF8A1E Halftone RAM, 16 words, one per halftone line.
HARDWARE QUIRKS
-------------------------------------------------------------------
Read-modify-write happens whenever an endmask is not all ones.
Atari's own documentation states NFSR can also trigger this;
Hatari's authors state that is wrong and only the mask does.
In non-hog mode the blitter sometimes uses only 63 bus accesses
rather than 64, if the CPU makes a bus access during the 4-cycle
latency after the busy bit is set.
With x count = 1 and NFSR set, real STE and Falcon hardware
produce results that depend on whether the source X increment is
positive or negative. Emulated correctly since 2020, but treat
that combination as best avoided.
Back to Memory Map for Atari ST,STE,TT and Falcon