IDE, Memory control & video

===========#==#=======#===============================================#===== ----------------------|IDE Bus |----- ===========#==#=======#===============================================#===== $FFF00000.W|RW|IDE_DAT|Data Register |

$FFF00005.B|RW|IDE_ERR|Read:Error / Write:Features Register |

$FFF00005 IDE_ERR Error Register (read) / Features (write) READ - error register, valid when the error bit is set in the status register at $FFF0001D: Bit 7 Bad Block Mark Bit 6 Uncorrectable Error Bit 5 (reserved) Bit 4 ID Field Not Found Bit 3 (reserved) Bit 2 Command Aborted Bit 1 Track 0 Not Found Bit 0 DAM (Data Address Mark) Not Found WRITE - features register, command specific. Used mainly by SET FEATURES to enable or disable drive options. Bit assignments from the Atari Compendium, matching the standard ATA error register layout.

$FFF00019.B|RW|IDE_H_D|Head/Drive Register |

$FFF00019 IDE_H_D Drive / Head Register Bit 7 (always 1 on early ATA) Bit 6 0 = CHS addressing, 1 = LBA addressing Bit 5 (always 1 on early ATA) Bit 4 Drive select: 0 = master, 1 = slave Bits 3-0 Head number, 0-15 In LBA mode bits 3-0 carry LBA bits 27-24 instead of the head number. Drive select and head number from the Atari Compendium. The addressing and reserved bits follow the standard ATA layout.

$FFF00042.B|RW| - |Add-on control, not present on stock hardware |*

$FFF00042 and $FFF00044 Add-on control registers Not present on stock Atari hardware. These sit in the same address space as the IDE interface above. Known to be used by: TRUDIE. TRUDIE also claims $FFF00000 to $FFF00038, which is the IDE register range itself, and $FFFFFFFF. POSSIBLE CONFLICT, NOT YET VERIFIED: other IDE solutions such as MONSTER use this same address space, and EmuTOS has its own built in IDE driver. An EmuTOS IDE driver may not set the bits an add-on needs to operate correctly. Anyone using more than one of these together should check for collisions. Extended bit information is not currently available for these registers. The addresses are documented; what each bit does is not.

$FFF00044.B|RW| - |Add-on control, not present on stock hardware |* ===========#==#=======#===============================================#===== ----------------------|Memory Controller, System Control |----- ===========#==#=======#===============================================#=====

$FFFF8001.B|RW|MEM_CTL|Memory Controller |

$FFFF8001 MEM_CTL Memory Controller Configuration Bits 3-2 Bank 1 size Bits 1-0 Bank 0 size Size encoding, same for both banks: 00 = 128k 01 = 512k 10 = 2M 11 = reserved A shadow copy of this byte is kept in the system variable memcntlr at $00000424, validated by memval2 at $0000043A. Bit assignments from the Atari Compendium.

$FFFF8006.W|RW|SYS_CTL|System Control %MM______ _RS_bB_C |F | | | Monitor Type (M0,M1)--------++ || || | |F | | | Monochrome Monitor----------00 || || | |F | | | RGB Monitor-----------------01 || || | |F | | | VGA Monitor-----------------10 || || | |F | | | TV--------------------------11 || || | |F | | | Reset 0:ignore resetvector------------+| || | |F | | | STE-compatible-I/O 0:off,1:on----------+ || | |F | | | Blitterflag 0:on,1:off-------------------+| | |F | | | Blitterspeed 0:half clock,1:full clock----+ | |F | | | CPUspeed 0:half clock,1:full clock----------+ |F

$FFFF8006 SYS_CTL System Control / Connected Monitor Type Bits 15-14, monitor type: 0 = Atari monochrome 1 = Atari colour (RGB) 2 = VGA colour 3 = television Bit 9 Reset: 0 = ignore reset vector Bit 8 STE compatible I/O: 0 = off, 1 = on Bit 6 Blitter flag: 0 = on, 1 = off Bit 5 Blitter speed: 0 = half clock, 1 = full clock Bit 3 CPU speed: 0 = half clock, 1 = full clock Monitor bits confirmed by Atari TOS 4.04, which tests (byte >> 6) & 3 == 0 to detect a monochrome monitor, and by the Atari Compendium value table. Falcon only. On earlier machines monitor detection is through MFP GPIP bit 7 at $FFFFFA01.

$FFFF8007.B|RW|SYS_FBC|Falcon Bus Control %_SB_BS__ |F | | | Start type 0:cold,1:warm-------------+||||||| | | | | STe Bus emulation 0:on,1:off----------+|||||| | | | | Blitter control 0:on,1:off--------------+|||| | | | | Blitter speed 0:8MHz,1:16MHz-------------+||| | | | | CPU speed 0:8MHz,1:16MHz--------------------+ | | | | Verified: EmuTOS bios/machine.c documents all | | | | five bits and writes $25 (STe bus emulation | | | | off, 16MHz blitter and CPU). Atari TOS | | | | 3.06/4.04 bios/startup.S writes the same $25. |

$FFFF8007 SYS_FBC Falcon Bus Control Bit 6 Start type: 0 = cold start, 1 = warm start Bit 5 STe Bus emulation: 0 = on, 1 = off Bit 3 Blitter control: 0 = on, 1 = off Bit 2 Blitter speed: 0 = 8MHz, 1 = 16MHz Bit 0 CPU speed: 0 = 8MHz, 1 = 16MHz STe bus emulation has to be switched off for bus-error based hardware detection to work on the Falcon. EmuTOS bios/machine.c documents all five bits and writes $25, setting STe bus emulation off with 16MHz blitter and CPU. Atari TOS 3.06/4.04 bios/startup.S writes the same $25 and tests bit 6. Falcon only.

===========#==#=======#===============================================#===== ----------------------|DMA, VIDEL Controller |----- ===========#==#=======#===============================================#===== $FFFF8201.B|RW|VDL_VBH|Video Base Hi | $FFFF8203.B|RW|VDL_VBM|Video Base Mi | $FFFF8205.B|Rw|VDL_VCH|Video Count Hi | $FFFF8207.B|Rw|VDL_VCM|Video Count Mi | $FFFF8209.B|Rw|VDL_VCL|Video Count Lo %xxxxxxx_ |

$FFFF820A VDL_SYM Video Shifter Sync Mode Bit 1 Vertical frequency: 0 = 60Hz (NTSC), 1 = 50Hz (PAL) Bit 0 Sync source: 0 = internal, 1 = external Setting bit 0 stops the shifter generating its own sync and makes it follow an external signal. This is the register used for the classic sync-switching border removal tricks: writing it at a precise point in the scanline makes the shifter miss the border, opening the display area. Bit assignments from the Atari Compendium.

$FFFF8240.W|RW|VDL_STC|ST Palette Register 00 %____rRRR gGGGbBBB |

$FFFF8240 to $FFFF825E ST/STE Palette Registers 0-15 Word registers, one per palette entry. ST layout: XXXX XRRR XGGG XBBB (3 bits per gun, 512 colours) STE layout: XXXX RRRR GGGG BBBB (4 bits per gun, 4096 colours) IMPORTANT: on the STE the four bits within each nibble are NOT in natural order. The bit arrangement per nibble is 0-3-2-1. The extra bit the STE adds is placed at the TOP of the nibble rather than the bottom, so that an ST program writing only the lower three bits still produces the same colour it would on an ST. Reading an STE palette value as a plain 4 bit number gives the wrong intensity. Hatari masks writes to $0777 on an ST and $0FFF on an STE. Some games write $FFFF and read the value back to detect whether they are running on an STE. These registers are simulated for compatibility on the TT and Falcon, which have their own wider palettes at $FFFF8400 and $FFFF9800. Layout and nibble ordering from the Atari Compendium, masking behaviour from Hatari src/video.c.

...........|RW| - |...................... | $FFFF825E.W|RW| - |ST Palette Register 15 |

$FFFF8260.B|RW|VDL_SSM|ST-Shift-Mode %_____xxx | | | | 320*200*4---------------------------------000 | | | | 640*200*2---------------------------------001 | | | | 640*400*1---------------------------------010 |

$FFFF8260 VDL_SSM ST Video Shifter Mode Bits 1-0 resolution 00 = 320x200, 4 planes (low) 01 = 640x200, 2 planes (medium) 10 = 640x400, 1 plane (high) 11 = reserved The TT modes were previously listed here. Atari uses a separate TT shifter register at $FFFF8262. A shadow copy of the current value is kept in the system variable sshiftmd at $0000044C. Writing 11 is not a documented mode. On real hardware it produces the same output as one of the other modes rather than anything useful; neither Atari TOS nor EmuTOS ever writes it. Bit assignments from the Atari Compendium and Atari TOS bios/startup.S.

===========#==#=======#===============================================#=====

$FFFF8262.B|RW|VDL_TSM|TT-Shift-Mode %_____xxx |TT | | | ST low 320*200*4----------------------000 |TT | | | ST medium 640*200*2----------------------001 |TT | | | ST high 640*400*1----------------------010 |TT | | | (Falcon rez marker)-----------------------011 |TT | | | TT medium 640*480*4----------------------100 |TT | | | (unused)----------------------------------101 |TT | | | TT high 1280*960*1----------------------110 |TT | | | TT low 320*480*8----------------------111 |TT

$FFFF8262 VDL_TSM TT Video Shifter Mode Word register. The byte at $FFFF8262 is the high half: Bit 7 Special video mode Bit 4 Special video mode Bits 2-0 resolution 000 = 320x200, 4 planes ST low 001 = 640x200, 2 planes ST medium 010 = 640x400, 1 plane ST high 011 = (Falcon rez marker) 100 = 640x480, 4 planes TT medium 101 = (unused) 110 = 1280x960, 1 plane TT high 111 = 320x480, 8 planes TT low The byte at $FFFF8263 is the low half and holds the ST Palette Bank, selecting which 16 entry bank of the 256 entry TT palette the ST compatible palette registers map onto. The two special video mode bits are named Smear Mode and Hyper Mono Mode by the Atari Compendium. CHECK: which name goes with which bit is not certain from the available sources. Hatari masks both together as 0x90 without naming them individually. Atari TOS 3.06 bios/startup.S declares this register as shift_tt and defines TTMED=4, TTHIGH=6, TTLOW=7. When the resolution is 2 or lower, Hatari mirrors the value into $FFFF8260 so the ST shifter register stays consistent. Resolution values from Atari TOS source, bit positions from Hatari src/video.c, names from the Atari Compendium.

$FFFF8266.W|RW|VDL_FSM|Falcon Shift Mode %_____2OT _HV8PPPP |F | | | 2 Color mode 0:off,1:on----------+|| ||||||| |F | | | Overlay mode 0:off,1:on-----------+| ||||||| |F | | | True(high) color 0:off,1:on--------+ ||||||| |F | | | Hsync 0:internal,1:external-----------+|||||| |F | | | Vsync 0:internal,1:external------------+||||| |F | | | 8 Bitplanes 0:off,1:on------------------+|||| |F | | | falcon Palette 16 of 256 colors----------++++ |F

$FFFF8266 VDL_FSM SPSHIFT / Falcon Shift Mode Bit 10 Enable 2-colour mode Bit 8 Enable truecolor mode Bit 6 Use external HSYNC Bit 5 Use external VSYNC Bit 4 Enable bitplane mode (8 bitplanes) Bits 3-0 Falcon palette bank, 16 of 256 colours Bit 9 is the overlay mode bit. Only one of the mode bits should be set at a time. Truecolor mode takes the pixel value straight to the DAC and ignores the palette entirely. Atari TOS 4.04 (tos3x bios/vsetmode.c) writes $0100 to select truecolor and $0010 to select 8 bitplane mode, confirming bits 8 and 4. Bit meanings from the Atari Compendium, confirmed against Atari TOS 4.04 and EmuTOS.

$FFFF827E STY_DSP STACY Display State Bit 1 1 = backlight off Bit 0 1 = display off STACY only, the portable ST. Rare hardware. UNVERIFIED: Atari Compendium only. Not referenced by EmuTOS, Hatari or any available TOS source.

$FFFF8280.W|RW|VDL_HHC|Horizontal Hold Counter %_______x xxxxxxxx |F $FFFF8282.W|RW|VDL_HHT|Horizontal Hold Timer %_______x xxxxxxxx |F $FFFF8284.W|RW|VDL_HBB|Horizontal Border Begin %_______x xxxxxxxx |F $FFFF8286.W|RW|VDL_HBE|Horizontal Border End %_______x xxxxxxxx |F $FFFF8288.W|RW|VDL_HDB|Horizontal Display Begin %______Hx xxxxxxxx |F | | | 0:1.Halfline, 1:2.Halfline--------+ |F $FFFF828A.W|RW|VDL_HDE|Horizontal Display End %_______x xxxxxxxx |F $FFFF828C.W|RW|VDL_HSS|Horizontal Sync Start %_______x xxxxxxxx |F $FFFF828E.W|RW|VDL_HFS|Horizontal FS %_______x xxxxxxxx |F $FFFF8290.W|RW|VDL_HEE|Horizontal EE %_______x xxxxxxxx |F $FFFF82A0.W|RW|VDL_VFC|Vertical Frequency Counter %_____xxx xxxxxxxx |F $FFFF82A2.W|RW|VDL_VFT|Vertical Frequency Timer %_____xxx xxxxxxxx |F $FFFF82A4.W|RW|VDL_VBB|Vertical Border Begin %_____xxx xxxxxxxx |F $FFFF82A6.W|RW|VDL_VBE|Vertical Border End %_____xxx xxxxxxxx |F $FFFF82A8.W|RW|VDL_VDB|Vertical Display Begin %_____xxx xxxxxxxx |F $FFFF82AA.W|RW|VDL_VDE|Vertical Display End %_____xxx xxxxxxxx |F $FFFF82AC.W|RW|VDL_VSS|Vertical Sync Start %_____xxx xxxxxxxx |F $FFFF82C0.W|RW|VDL_VCT|Video Control %_______O BHVUSCMM |F | | | h-base-Offset 0:128cyc,1:64cyc-----+ |||||||| |F | | | Buswide 0:16bit,1:32bit--------------+||||||| |F | | | Hsync 0:negative,1:positive-----------+|||||| |F | | | Vsync 0:negative,1:positive------------+||||| |F | | | Use FS & EE 0:on,1:off------------------+|||| |F | | | 15 halfline hSyncs at VBB----------------+||| |F | | | video Clock 0:32Mhz,1:25.175Mhz-----------+|| |F | | | Monitor 0:Mono,1:RGB,2:VGA,3:TV------------++ |F | | | NAMING CHECK: TOS 4.04 (tos3x vsetmode.c) and |F | | | EmuTOS write video_control to $82C2 and |F | | | video_clock to $82C0 - the reverse of these |F | | | two labels. Addresses/bits correct either way.|F

$FFFF82C2.W|RW|VDL_VMD|Video Mode %________ ____xxID |F | | | Pixclock:4,Divider:4(VGA)/16(STE)/4------00|| |F | | | Pixclock:2,Divider:2(VGA)/16(STE)/2------01|| |F | | | Pixclock:1,Divider:2(VGA)/16(STE)/1------10|| |F | | | (unused)---------------------------------11|| |F | | | Interlace 0:off,1:on-----------------------+| |F | | | Double Scan 0:off,1:on----------------------+ |F

$FFFF82C2 VDL_VMD VCO / Video Mode Bit 3 Quarter pixel width Bit 2 Halve pixel width Bit 1 Interlace mode Bit 0 Line doubling Bits 3-2 together give the pixel clock divider: 00 = full width (divider 4 on VGA, 16 on STE) 01 = half width (divider 2 on VGA, 16 on STE) 10 = quarter width(divider 2 on VGA, 16 on STE) 11 = not used, never written by TOS or EmuTOS Line doubling and interlace are mutually exclusive: line doubling is used on VGA to display a 200 line mode at 400 lines, interlace on television output. NAMING CHECK: Atari TOS 4.04 (tos3x bios/vsetmode.c) writes video_control to $FFFF82C2 and video_clock to $FFFF82C0, and EmuTOS uses the same naming. That is the reverse of the labels used on this page. The addresses and bit layouts are confirmed correct by both sources; only the register names may be the wrong way round. Bit assignments from the Atari Compendium, confirmed against Atari TOS 4.04 and EmuTOS.

===========#==#=======#===============================================#===== ----------------------|TT Palette Registers |----- ===========#==#=======#===============================================#=====

$FFFF8400.W|RW|TT__PAL|TT Palette Register 000 |TT

$FFFF8400 to $FFFF85FE TT Palette Registers 0-255 Word registers, one per palette entry, 256 entries. Layout: XXXX RRRR GGGG BBBB Unlike the ST and STE registers at $FFFF8240, each nibble here is in natural order, 3-2-1-0. There is no compatibility reordering. The ST compatible palette registers at $FFFF8240 map onto a 16 entry bank of this palette, selected by the ST Palette Bank field in the low byte of $FFFF8262. TT only. Layout from the Atari Compendium.

...........|RW| - |....................... |TT $FFFF85FE.W|RW| - |TT Palette Register 255 |TT ===========#==#=======#===============================================#===== ----------------------|VIDEL Palette Register |----- ===========#==#=======#===============================================#=====

$FFFF9800.L|RW|VDL_PAL|Palette Register 000 %RRRRRR__ GGGGGG__ |F

$FFFF9800 to $FFFF98FC VIDEL Palette Registers 0-255 Longword registers, one per palette entry, 256 entries. Layout, across the four bytes of each longword: Byte 0 RRRRRR-- red, 6 bits Byte 1 GGGGGG-- green, 6 bits Byte 2 -------- unused Byte 3 BBBBBB-- blue, 6 bits Six bits per gun, so 262144 possible colours, of which 256 can be displayed at once. The low two bits of each byte are unused and read back as zero. Falcon only. Ignored entirely in truecolor mode, where the pixel value goes straight to the DAC. Layout from the Atari Compendium.

...........|RW| - |.................... ________ BBBBBB__ |F $FFFF98FC.L|RW| - |Palette Register 255 |F ===========#==#=======#===============================================#===== ----------------------|DMA, Blitter |----- ===========#==#=======#===============================================#===== $FFFF8A00.W|RW|BLT_HTR|Halftone-RAM 00 |BLT ...........|RW| - |............... |BLT $FFFF8A1E.W|RW| - |Halftone-RAM 15 |BLT $FFFF8A20.W|RW|BLT_SXI|Source X increment %xxxxxxxx xxxxxxx_ |BLT $FFFF8A22.W|RW|BLT_SYI|Source Y increment %xxxxxxxx xxxxxxx_ |BLT $FFFF8A24.L|RW|BLT_SRC|Source Address %xxxxxxxx xxxxxxxx xxxxxxx_ |BLT $FFFF8A28.W|RW|BLT_EM1|Endmask 1 |BLT $FFFF8A2A.W|RW|BLT_EM2|Endmask 2 |BLT $FFFF8A2C.W|RW|BLT_EM3|Endmask 3 |BLT $FFFF8A2E.W|RW|BLT_DXI|Destination X increment %xxxxxxxx xxxxxxx_ |BLT $FFFF8A30.W|RW|BLT_DYI|Destination Y increment %xxxxxxxx xxxxxxx_ |BLT $FFFF8A32.L|RW|BLT_DST|Destination Adr. %xxxxxxxx xxxxxxxx xxxxxxx_ |BLT $FFFF8A36.W|RW|BLT_WPL|Words per Line in BOB (0:65536)|BLT $FFFF8A38.W|RW|BLT_LPB|Lines per BOB (0:65536)|BLT

$FFFF8A3A.B|RW|BLT_HTO|Halftone Operation %______xx |BLT | | | 0:set all Bits, 1:HTR, 2:SRC, 3:SRC & HTR |BLT

$FFFF8A3A BLT_HTO Halftone Operation, bits 1-0 0 all ones ($FFFF) 1 halftone RAM word 2 source word 3 source word AND halftone RAM word HOP runs first, LOP second. The HOP result is what the logical operation sees as its "source" input. Verified against Hatari src/blitter.c.

$FFFF8A3B.B|RW|BLT_LGO|Logical Operation %____xxxx |BLT | | | (!S AND !D)------------------------------+||| |BLT | | | (!S AND D)-------------------------------+|| |BLT | | | ( S AND !D)--------------------------------+| |BLT | | | ( S AND D)---------------------------------+ |BLT

$FFFF8A3B BLT_LGO Logical Operation, bits 3-0 S = output of the halftone operation above D = current destination word $0 all zeros $8 NOT S AND NOT D (NOR) $1 S AND D $9 NOT (S XOR D) (NXOR) $2 S AND NOT D $A NOT D $3 S $B S OR NOT D $4 NOT S AND D $C NOT S $5 D $D NOT S OR D $6 S XOR D $E NOT (S AND D) (NAND) $7 S OR D $F all ones The register takes a value 0-15 selecting one of sixteen operations, not just the four AND combinations shown above. Verified against Hatari src/blitter.c.

$FFFF8A3C.B|RW|BLT_LNM|Line Number %BHS_xxxx |BLT | | | Busy (1:start Blitter)---------------+|| |||| |BLT | | | HOG (1:stop CPU when Busy)------------+| |||| |BLT | | | SMUDGE (use sourcebits 0-3 as HTR num)-+ |||| |BLT | | | Halftone-RAM number----------------------++++ |BLT

$FFFF8A3C BLT_LNM Control, %BHS_nnnn Bit 7 BUSY write 1 to start the blitter. Reads 1 while a transfer is in progress, cleared when y count reaches 0. Bit 6 HOG 0 = share the bus with the CPU, 1 = take the bus for the whole transfer. Bit 5 SMUDGE use source bits 0-3 as the halftone line number instead of bits 3-0 of this register. Bit 4 unused. Hardware masks this bit off on write. Bits 3-0 halftone line number, 0-15. In non-hog mode the blitter runs for 64 bus accesses, then hands the bus to the CPU for 64. Writing 0 to bit 7 while the CPU owns the bus pauses the blitter; writing 1 resumes it. Pausing does not end the transfer, and busy still reads 1. Quirk: in non-hog mode the blitter sometimes uses only 63 bus accesses rather than 64, if the CPU makes a bus access during the 4-cycle latency after the busy bit is set. Verified against Hatari src/blitter.c.

$FFFF8A3D.B|RW|BLT_SKW|SKEW %FN__xxxx |BLT | | | FXSR (Force eXtra Source Read)-------+| |||| |BLT | | | NFSR (No Final Source Read)-----------+ |||| |BLT | | | SKEW (shift)-----------------------------++++ |BLT

$FFFF8A3D BLT_SKW Skew, %FN__nnnn Bit 7 FXSR Force eXtra Source Read Bit 6 NFSR No Final Source Read Bits 5-4 unused Bits 3-0 skew, 0-15 pixels Read-modify-write happens whenever an endmask is not all ones. Atari's own documentation states NFSR can also trigger this; Hatari's authors state that is wrong and only the mask does. Quirk: with x count = 1 and NFSR set, real STE and Falcon hardware produce results that depend on whether the source X increment is positive or negative. Verified against Hatari src/blitter.c.

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